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PD - 96906B
IRFB4610 IRFS4610 IRFSL4610
Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits Benefits l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability
G S
HEXFET(R) Power MOSFET
D
VDSS RDS(on) typ. max. ID
100V 11m: 14m: 73A
GDS
TO-220AB IRFB4610
GDS
D2Pak IRFS4610
GDS
TO-262 IRFSL4610
Absolute Maximum Ratings
Symbol
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS dV/dt TJ TSTG
Parameter
Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current f Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery e Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw
Max.
73 52 290 190 1.3 20 7.6 -55 to + 175 300 10lbxin (1.1Nxm)
Units
A
W W/C V V/ns C
Avalanche Characteristics
EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy d Avalanche Current c Repetitive Avalanche Energy f 370 See Fig. 14, 15, 16a, 16b, mJ A mJ
Thermal Resistance
Symbol
RJC RCS RJA RJA
Parameter
Junction-to-Case j Case-to-Sink, Flat Greased Surface , TO-220 Junction-to-Ambient, TO-220 j Junction-to-Ambient (PCB Mount) , D2Pak ij
Typ.
--- 0.50 --- ---
Max.
0.77 --- 62 40
Units
C/W
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1
11/3/04
IRF/B/S/SL4610
Static @ TJ = 25C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Drain-to-Source Breakdown Voltage
Min. Typ. Max. Units
100 --- --- 2.0 --- --- --- --- --- --- 0.085 11 --- --- --- --- --- 1.5 --- --- 14 4.0 20 250 200 -200 --- nA V
Conditions
VGS = 0V, ID = 250A
V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance VGS(th) IDSS IGSS RG Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Gate Input Resistance
V/C Reference to 25C, ID = 1mAc m VGS = 10V, ID = 44A f V A VDS = VGS, ID = 100A VDS = 100V, VGS = 0V VDS = 100V, VGS = 0V, TJ = 125C VGS = 20V VGS = -20V f = 1MHz, open drain
Dynamic @ TJ = 25C (unless otherwise specified)
Symbol
gfs Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss
Parameter
Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance
Min. Typ. Max. Units
73 --- --- --- --- --- --- --- --- --- --- 90 20 36 18 87 53 70 3550 260 150 330 380 --- 140 --- --- --- --- --- --- --- --- --- --- --- pF ns S nC ID = 44A VDS = 80V VGS = 10V f VDD = 65V ID = 44A RG = 5.6 VGS = 10V f VGS = 0V VDS = 50V = 1.0MHz
Conditions
VDS = 50V, ID = 44A
Reverse Transfer Capacitance --- Coss eff. (ER) Effective Output Capacitance (Energy Related) --- Coss eff. (TR) Effective Output Capacitance (Time Related) ---
VGS = 0V, VDS = 0V to 80V h, See Fig.11 VGS = 0V, VDS = 0V to 80V g, See Fig. 5
Diode Characteristics
Symbol
IS ISM VSD trr Qrr IRRM ton
Parameter
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) c Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time
Min. Typ. Max. Units
--- --- --- --- --- --- --- --- --- --- --- 35 42 44 65 2.1 73 290 1.3 53 63 66 98 --- A nC V ns A
Conditions
MOSFET symbol showing the integral reverse p-n junction diode. TJ = 25C, IS = 44A, VGS = 0V f VR = 85V, TJ = 25C TJ = 125C TJ = 25C TJ = 125C TJ = 25C IF = 44A di/dt = 100A/s f
G S D
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes: Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25C, L = 0.39mH RG = 25, IAS = 44A, VGS =10V. Part not recommended for use above this value. ISD 44A, di/dt 660A/s, VDD V(BR)DSS, TJ 175C. Pulse width 400s; duty cycle 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as When mounted on 1" square PCB (FR-4 or G-10 Material). For recom R is measured at TJ approximately 90C
Coss while VDS is rising from 0 to 80% VDSS. mended footprint and soldering techniques refer to application note #AN-994.
2
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IRF/B/S/SL4610
1000
TOP VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V
1000
TOP VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V
ID, Drain-to-Source Current (A)
100
BOTTOM
ID, Drain-to-Source Current (A)
BOTTOM
100
10
4.5V 60s PULSE WIDTH Tj = 25C
4.5V 60s PULSE WIDTH Tj = 25C
10 0.1 1 10 100
1 0.1 1 10 100
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1000.0
3.0
Fig 2. Typical Output Characteristics
RDS(on) , Drain-to-Source On Resistance (Normalized)
ID = 73A
2.5
ID, Drain-to-Source Current()
VGS = 10V
100.0
TJ = 175C
10.0
2.0
1.5
1.0
TJ = 25C VDS = 25V
1.0
60s PULSE WIDTH
0.1 2.0 3.0 4.0 5.0 6.0 7.0 8.0
0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
VGS, Gate-to-Source Voltage (V)
TJ , Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
6000 VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd Coss = Cds + Cgd
Fig 4. Normalized On-Resistance vs. Temperature
20
VGS, Gate-to-Source Voltage (V)
ID= 44A VDS = 80V VDS= 50V VDS= 20V
5000
16
C, Capacitance (pF)
4000
Ciss
12
3000
8
2000
4
1000
Coss Crss
1 10 100
0
0 0 20 40 60 80 100 120 140 QG Total Gate Charge (nC)
VDS , Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRF/B/S/SL4610
1000.0
1000
ID, Drain-to-Source Current (A)
OPERATION IN THIS AREA LIMITED BY R DS (on) 100sec
ISD , Reverse Drain Current (A)
100.0
TJ = 175C
100
10.0
10
1msec 10msec Tc = 25C Tj = 175C Single Pulse
TJ = 25C
1.0
1
VGS = 0V
0.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
DC 10 100 1000
0.1 1
VSD , Source-to-Drain Voltage (V)
VDS , Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
80
Fig 8. Maximum Safe Operating Area
V(BR)DSS , Drain-to-Source Breakdown Voltage
125
ID , Drain Current (A)
60
120
115
40
110
20
105
0 25 50 75 100 125 150 175
100 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (C)
TJ , Junction Temperature (C)
Fig 9. Maximum Drain Current vs. Case Temperature
2.0
Fig 10. Drain-to-Source Breakdown Voltage
1600
EAS, Single Pulse Avalanche Energy (mJ)
1.5
1200
ID 4.6A 6.3A BOTTOM 44A
TOP
Energy (J)
1.0
800
0.5
400
0.0 0 20 40 60 80 100
0 25 50 75 100 125 150 175
VDS, Drain-to-Source Voltage (V)
Starting TJ, Junction Temperature (C)
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
4
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IRF/B/S/SL4610
1
D = 0.50
Thermal Response ( Z thJC )
0.1
0.20 0.10 0.05 0.02
R1 R1 J 1 2 R2 R2 C 2
0.01
0.01
J
Ri (C/W) i (sec) 0.4367 0.001016 0.3337 0.009383
1
0.001
Ci= i/Ri Ci i/Ri
SINGLE PULSE ( THERMAL RESPONSE )
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc
0.0001 0.001 0.01 0.1
0.0001 1E-006 1E-005
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Duty Cycle = Single Pulse
Avalanche Current (A)
100
0.01
10
0.05 0.10
Allowed avalanche Current vs avalanche pulsewidth, tav assuming Tj = 25C due to avalanche losses. Note: In no case should Tj be allowed to exceed Tjmax
1
0.1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
400
EAR , Avalanche Energy (mJ)
300
TOP Single Pulse BOTTOM 1% Duty Cycle ID = 44A
200
100
Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
175
0 25 50 75 100 125 150
Starting TJ , Junction Temperature (C)
PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRF/B/S/SL4610
5.0
16
VGS(th) Gate threshold Voltage (V)
4.0
ID = 1.0A ID = 1.0mA ID = 250A ID = 100A
IRRM - (A)
12
3.0
8
2.0
4
IF = 29A VR = 85V TJ = 125C TJ = 25C 100 200 300 400 500 600 700 800 900 1000
1.0 -75 -50 -25 0 25 50 75 100 125 150 175
0
TJ , Temperature ( C )
dif / dt - (A / s)
Fig 16. Threshold Voltage Vs. Temperature
16
Fig. 17 - Typical Recovery Current vs. dif/dt
300
12
200
8
QRR - (nC)
100
IRRM - (A)
4
IF = 44A VR = 85V TJ = 125C TJ = 25C
IF = 29A VR = 85V TJ = 125C TJ = 25C 100 200 300 400 500 600 700 800 900 1000
0 100 200 300 400 500 600 700 800 900 1000
0
dif / dt - (A / s)
dif / dt - (A / s)
Fig. 18 - Typical Recovery Current vs. dif/dt
300
Fig. 19 - Typical Stored Charge vs. dif/dt
200
QRR - (nC)
100
IF = 44A VR = 85V TJ = 125C TJ = 25C 100 200 300 400 500 600 700 800 900 1000
0
dif / dt - (A / s)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRF/B/S/SL4610
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
* * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage
Body Diode
Forward Drop
Inductor Curent Inductor Current
Ripple 5% ISD
* VGS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs
V(BR)DSS
15V
tp
DRIVER
VDS
L
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
A
0.01
I AS
Fig 22a. Unclamped Inductive Test Circuit
LD VDS
Fig 22b. Unclamped Inductive Waveforms
+
VDD D.U.T VGS Pulse Width < 1s Duty Factor < 0.1%
90%
VDS
10%
VGS
td(on) tr td(off) tf
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Id Vds Vgs
L
0
DUT 1K
VCC
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
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Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
7
IRF/B/S/SL4610
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
2.87 (.113) 2.62 (.103) 10.54 (.415) 10.29 (.405) 3.78 (.149) 3.54 (.139) -A6.47 (.255) 6.10 (.240) -B4.69 (.185) 4.20 (.165) 1.32 (.052) 1.22 (.048)
4 15.24 (.600) 14.84 (.584)
1.15 (.045) MIN 1 2 3
LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN
14.09 (.555) 13.47 (.530)
4.06 (.160) 3.55 (.140)
3X 1.40 (.055) 3X 1.15 (.045) 2.54 (.100) 2X NOTES:
0.93 (.037) 0.69 (.027) M BAM
3X
0.55 (.022) 0.46 (.018)
0.36 (.014)
2.92 (.115) 2.64 (.104)
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH
3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
E XAMPL E : T HIS IS AN IR F 1010 L OT CODE 1789 AS S E MB L E D ON WW 19, 1997 IN T H E AS S E MB L Y L INE "C" INT E R NAT IONAL R E CT IF IE R L OGO AS S E MB L Y L OT CODE PAR T NU MB E R
Note: "P" in assembly line position indicates "Lead-Free"
DAT E CODE YE AR 7 = 1997 WE E K 19 L INE C
TO-220AB packages are not recommended for Surface Mount Application.
8
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IRF/B/S/SL4610
TO-262 Package Outline (Dimensions are shown in millimeters (inches))
IGBT 1- GATE 2- COLLECTOR 3- EMITTER 4- COLLECTOR
TO-262 Part Marking Information
EXAMPLE: THIS IS AN IRL3103L LOT CODE 1789 AS SEMBLED ON WW 19, 1997 IN THE ASS EMBLY LINE "C" Note: "P" in as sembly line pos ition indicates "Lead-Free" INTERNATIONAL RECTIFIER LOGO ASS EMBLY LOT CODE PART NUMBER
DAT E CODE YEAR 7 = 1997 WEEK 19 LINE C
OR
INT ERNATIONAL RECTIFIER LOGO AS SEMBLY LOT CODE PART NUMBER DAT E CODE P = DES IGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 7 = 1997 WEEK 19 A = AS SEMBLY SITE CODE
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9
IRF/B/S/SL4610
D2Pak Package Outline (Dimensions are shown in millimeters (inches))
D2Pak Part Marking Information
T HIS IS AN IRF530S WITH LOT CODE 8024 AS S EMBLED ON WW 02, 2000 IN T HE AS S EMBLY LINE "L" Note: "P" in assembly line pos ition indicates "Lead-Free" INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER F530S DAT E CODE YEAR 0 = 2000 WEEK 02 LINE L
OR
INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE
PART NUMBER F530S DAT E CODE P = DES IGNAT ES LEAD-FREE PRODUCT (OPT IONAL) YEAR 0 = 2000 WEEK 02 A = AS S EMBLY S IT E CODE
10
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IRF/B/S/SL4610
D2Pak Tape & Reel Information
TRR
1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153)
1.60 (.063) 1.50 (.059)
0.368 (.0145) 0.342 (.0135)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
11.60 (.457) 11.40 (.449)
15.42 (.609) 15.22 (.601)
24.30 (.957) 23.90 (.941)
TRL
10.90 (.429) 10.70 (.421) 1.75 (.069) 1.25 (.049) 16.10 (.634) 15.90 (.626) 4.72 (.136) 4.52 (.178)
FEED DIRECTION
13.50 (.532) 12.80 (.504)
27.40 (1.079) 23.90 (.941)
4
330.00 (14.173) MAX.
60.00 (2.362) MIN.
NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039) 24.40 (.961) 3
30.40 (1.197) MAX. 4
Data and specifications subject to change without notice. This product has been designed and qualified for the Automotive [Q101] market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 11/04
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